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» On the Processing of Decimated Signals
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DATE
2009
IEEE
135views Hardware» more  DATE 2009»
14 years 5 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
ICASSP
2008
IEEE
14 years 4 months ago
Blind optimization of algorithm parameters for signal denoising by Monte-Carlo SURE
We consider the problem of optimizing the parameters of an arbitrary denoising algorithm by minimizing Stein’s Unbiased Risk Estimate (SURE) which provides a means of assessing ...
Sathish Ramani, Thierry Blu, Michael Unser
DIS
1998
Springer
14 years 2 months ago
Automatic Transaction of Signal via Statistical Modeling
The statistical information processing can be characterized by the likelihood function de ned by giving an explicit form for an approximation to the true distribution. This mathema...
Genshiro Kitagawa, Tomoyuki Higuchi
HPCA
1997
IEEE
14 years 2 months ago
Datapath Design for a VLIW Video Signal Processor
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S....
ICASSP
2010
IEEE
13 years 10 months ago
A parallel point-process filter for estimation of goal-directed movements from neural signals
Brain machine interfaces work by mapping the relevant neural activity to the intended movement known as ‘decoding’. Here, we develop a recursive Bayesian decoder for goaldirec...
Maryam Modir Shanechi, Gregory W. Wornell, Ziv Wil...