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FPL
2006
Springer
99views Hardware» more  FPL 2006»
13 years 11 months ago
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
Daniel Ziener, Stefan Assmus, Jürgen Teich
ICFP
2012
ACM
11 years 10 months ago
Proof-producing synthesis of ML from higher-order logic
The higher-order logic found in proof assistants such as Coq and various HOL systems provides a convenient setting for the development and verification of pure functional program...
Magnus O. Myreen, Scott Owens
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 29 days ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
DSN
2008
IEEE
13 years 9 months ago
Detouring: Translating software to circumvent hard faults in simple cores
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
Albert Meixner, Daniel J. Sorin
NCA
2005
IEEE
14 years 1 months ago
C-CORE: Using Communication Cores for High Performance Network Services
Recent hardware advances are creating multi-core systems with heterogeneous functionality. This paper explores how applications and middleware can utilize systems comprised of pro...
Sanjay Kumar, Ada Gavrilovska, Karsten Schwan, Sri...