The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Abstract. We consider the single machine scheduling problem to minimize the average weighted completion time under precedence constrains. Improving on the various 2-approximation a...
This paper presents a comparison of power-aware video decoding techniques that utilize Dynamic Voltage Scaling (DVS) capability. Three techniques were simulated and compared in te...
Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Ki...