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» On the Utility of Threads for Data Parallel Programming
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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 2 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
CLUSTER
2009
IEEE
14 years 1 months ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis
SC
2005
ACM
14 years 2 months ago
The MHETA Execution Model for Heterogeneous Clusters
The availability of inexpensive “off the shelf” machines increases the likelihood that parallel programs run on heterogeneous clusters of machines. These programs are increasi...
Mario Nakazawa, David K. Lowenthal, Wenduo Zhou
ICPP
2002
IEEE
14 years 1 months ago
The Tracefile Testbed - A Community Repository for Identifying and Retrieving HPC Performance Data
HPC programmers utilize tracefiles, which record program behavior in great detail, as the basis for many performance analysis activities. The lack of generally accessible tracefil...
Ken Ferschweiler, Scott Harrah, Dylan Keon, Mariac...
IPPS
1999
IEEE
14 years 29 days ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...