333 search results - page 13 / 67 » On the complexity of partial order trace model checking |
ICECCS
2005
IEEE
14 years 1 months ago
2005
IEEE
Live Sequence Charts (LSCs) are a broad extension to Message Sequence Charts (MSCs) to capture complex interobject communication rigorously. A tool support for LSCs, named PlayEng...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...
FOSSACS
2001
Springer
14 years 1 days ago
2001
Springer
Hierarchical Message Sequence Charts are a well-established formalism to specify telecommunication protocols. In this model, numerous undecidability results were obtained recently ...
TACAS
2007
Springer
14 years 1 months ago
2007
Springer
For specifying and verifying branching-time requirements, a reactive system is traditionally modeled as a labeled tree, where a path in the tree encodes a possible execution of the...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...