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IPPS
2007
IEEE
14 years 4 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
IPPS
2007
IEEE
14 years 4 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
IWCMC
2006
ACM
14 years 3 months ago
Multi-hop CDMA cellular networks with power control
The concept of multi-hop CDMA cellular networks has been around for sometime now. It is a widely accepted assumption that using multi-hopping in cellular networks will increase th...
Ayman Radwan, Hossam S. Hassanein
DAC
2011
ACM
12 years 9 months ago
Efficient incremental analysis of on-chip power grid via sparse approximation
In this paper, a new sparse approximation technique is proposed for incremental power grid analysis. Our proposed method is motivated by the observation that when a power grid net...
Pei Sun, Xin Li, Ming Yuan Ting
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
14 years 10 months ago
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system compon...
Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim,...