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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 7 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
13 years 7 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
13 years 7 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
MM
2010
ACM
220views Multimedia» more  MM 2010»
13 years 7 months ago
Bateau ivre: an artistic markerless outdoor mobile augmented reality installation on a riverboat
Bateau Ivre is a project presented on the Seine River to make a large audience aware of the possible developments of Augmented Reality through an artistic installation in a mobile...
Christian Jacquemin, Wai Kit Chan, Matthieu Courge...
NOCS
2010
IEEE
13 years 7 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
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