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» On the energy-efficiency of speculative hardware
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MICRO
2007
IEEE
108views Hardware» more  MICRO 2007»
14 years 3 months ago
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
IEEEPACT
2002
IEEE
14 years 1 months ago
Eliminating Exception Constraints of Java Programs for IA-64
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komats...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 3 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
14 years 2 months ago
Energy-aware fetch mechanism: trace cache and BTB customization
1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
Daniel Chaver, Miguel A. Rojas, Luis Piñuel...
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
14 years 1 months ago
Analysis of power consumption in memory hierarchies
In this paper, we note and analyze a key trade-off: as the complexity of caches increases (higher set-associativity, larger block size, and larger overall size), the power consume...
Patrick Hicks, Matthew Walnock, Robert Michael Owe...