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» On the k-additive Core of Capacities
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FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 12 months ago
Detailed routing architectures for embedded programmable logic IP cores
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
Peter Hallschmid, Steven J. E. Wilton
HPCA
2009
IEEE
14 years 8 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
14 years 2 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
ICALT
2007
IEEE
14 years 1 months ago
A Conceptual Structure for Organizational Learning and Organizational Performance
This paper constructs a conceptual structure for organizational learning and organizational performance based on the core competitive capability view. Based on the research of org...
Li Zhang, Qiong Jia, Ping Li
HPCA
2011
IEEE
12 years 11 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...