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» On the k-additive Core of Capacities
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HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
LCN
2003
IEEE
14 years 20 days ago
An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks
Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the ...
Honglin Wu, Amir Gourgy, Ted H. Szymanski
ASMTA
2009
Springer
92views Mathematics» more  ASMTA 2009»
13 years 11 months ago
Comparison of Multi-service Routing Strategies for IP Core Networks
Abstract. Service differentiation in IP core networks may be supported by dedicated path selection rules. This paper investigates the degree of service distinction achievable when ...
Ulf Jensen, Armin Heindl
HPCA
2009
IEEE
14 years 8 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
IWQOS
2001
Springer
13 years 12 months ago
Dynamic Core Provisioning for Quantitative Differentiated Service
— Efficient network provisioning mechanisms that support service differentiation and automatic capacity dimensioning are essential to the realization of the Differentiated Servi...
Raymond R.-F. Liao, Andrew T. Campbell