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HIPEAC
2011
Springer
12 years 6 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
14 years 1 months ago
Multiple-Width Bus Partitioning Approach to Datapath Synthesis
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
Arash Ahmadi, Mark Zwolinski
CISSE
2008
Springer
13 years 8 months ago
Knowledge Assessment - Practical Example in Testing
: Knowledge assessment is inseparable part of current e-learning technologies. It can be used for self-assessment of students to give them feedback about their progress in a study ...
Ján Genci
CDC
2010
IEEE
147views Control Systems» more  CDC 2010»
12 years 10 months ago
Partial pole placement with minimum norm controller
— The problem of placing an arbitrary subset (m) of the (n) closed loop eigenvalues of a nth order continuous time single input linear time invariant(LTI) system, using full stat...
Subashish Datta, Balarko Chaudhuri, Debraj Chakrab...
HOTI
2008
IEEE
14 years 1 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...