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ISLPED
2003
ACM
88views Hardware» more  ISLPED 2003»
14 years 2 months ago
Reducing data cache energy consumption via cached load/store queue
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
14 years 1 months ago
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
Andreas Moshovos, Gurindar S. Sohi
CAV
1999
Springer
119views Hardware» more  CAV 1999»
14 years 1 months ago
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
Abstract. In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition ca...
Randal E. Bryant, Steven M. German, Miroslav N. Ve...
ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
14 years 5 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
VMCAI
2007
Springer
14 years 3 months ago
DIVINE: DIscovering Variables IN Executables
Abstract. This paper addresses the problem of recovering variable-like entities when analyzing executables in the absence of debugging information. We show that variable-like entit...
Gogul Balakrishnan, Thomas W. Reps