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» On the value locality of store instructions
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MICRO
2000
IEEE
61views Hardware» more  MICRO 2000»
14 years 3 days ago
Reducing wire delay penalty through value prediction
In this work we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating...
Joan-Manuel Parcerisa, Antonio González
MICRO
2002
IEEE
118views Hardware» more  MICRO 2002»
14 years 19 days ago
Exploiting data-width locality to increase superscalar execution bandwidth
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
Gabriel H. Loh
HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
13 years 11 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
HPCA
2004
IEEE
14 years 8 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
MICRO
2002
IEEE
114views Hardware» more  MICRO 2002»
14 years 19 days ago
Characterizing and predicting value degree of use
A value’s degree of use—the number of dynamic uses of that value—provides the most essential information needed to optimize its communication. We present simulation results ...
J. Adam Butts, Gurindar S. Sohi