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» On two-step routing for FPGAS
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VTS
1996
IEEE
111views Hardware» more  VTS 1996»
13 years 11 months ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
FPL
2007
Springer
178views Hardware» more  FPL 2007»
14 years 28 days ago
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavl...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
13 years 11 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
IH
1998
Springer
13 years 11 months ago
Fingerprinting Digital Circuits on Programmable Hardware
Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradig...
John Lach, William H. Mangione-Smith, Miodrag Potk...