Sciweavers

66 search results - page 7 / 14
» On-Chip Inductance in X Architecture Enabled Design
Sort
View
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 2 months ago
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
—The IEEE 802.15.4a amendment has introduced ultra-wideband impulse radio (UWB IR) as a promising physical layer for energy-efficient, low data rate communications. A critical p...
Christian Bachmann, Andreas Genser, Jos Hulzink, M...
LCTRTS
2010
Springer
14 years 2 months ago
Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing
Over the past decade, system architectures have started on a clear trend towards increased parallelism and heterogeneity, often resulting in speedups of 10x to 100x. Despite numer...
John Robert Wernsing, Greg Stitt
ENC
2004
IEEE
13 years 11 months ago
Distributed Learning in Intentional BDI Multi-Agent Systems
Despite the relevance of the belief-desire-intention (BDI) model of rational agency, little work has been done to deal with its two main limitations: the lack of learning competen...
Alejandro Guerra-Hernández, Amal El Fallah-...
MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
14 years 2 months ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
ARCS
2009
Springer
14 years 2 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...