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» On-chip logic minimization
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HPCA
2011
IEEE
13 years 1 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
FAST
2011
13 years 1 months ago
Leveraging Value Locality in Optimizing NAND Flash-based SSDs
: NAND flash-based solid-state drives (SSDs) are increasingly being deployed in storage systems at different levels such as buffer-caches and even secondary storage. However, the ...
Aayush Gupta, Raghav Pisolkar, Bhuvan Urgaonkar, A...
PLDI
2012
ACM
12 years 7 days ago
The implicit calculus: a new foundation for generic programming
Generic programming (GP) is an increasingly important trend in programming languages. Well-known GP mechanisms, such as type classes and the C++0x concepts proposal, usually combi...
Bruno C. d. S. Oliveira, Tom Schrijvers, Wontae Ch...
ISSTA
2012
ACM
12 years 6 days ago
Measuring enforcement windows with symbolic trace interpretation: what well-behaved programs say
A static analysis design is sufficient if it can prove the property of interest with an acceptable number of false alarms. Ultimately, the only way to confirm that an analysis d...
Devin Coughlin, Bor-Yuh Evan Chang, Amer Diwan, Je...