704 search results - page 1 / 141 » On-chip logic minimization |
DSD
2007
IEEE
14 years 13 days ago
2007
IEEE
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
ASAP
2004
IEEE
14 years 8 days ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
This paper presents an eļ¬cient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eļ¬...
DAC
1998
ACM
14 years 9 months ago
1998
ACM
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...