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CCE
2005
13 years 7 months ago
Use of parallel computers in rational design of redundant sensor networks
A general method to design optimal redundant sensor network even in the case of one sensor failure and able to estimate process key parameters within a required accuracy is propos...
Carine Gerkens, Georges Heyen
EUROPAR
1999
Springer
13 years 12 months ago
Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications
A fully adaptive router with hybrid bu ers at the input and output channels was designed, which improves the throughput of its input bu er counterpart by up to 40% and has only 10%...
Valentin Puente, José A. Gregorio, Cruz Izu...
DAC
2007
ACM
14 years 8 months ago
Layered Switching for Networks on Chip
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
Zhonghai Lu, Ming Liu, Axel Jantsch
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 2 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
AHS
2006
IEEE
124views Hardware» more  AHS 2006»
14 years 1 months ago
A Generic On-Chip Debugger for Wireless Sensor Networks
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
Andrew B. T. Hopkins, Klaus D. McDonald-Maier