36 search results - page 5 / 8 » One-Level Cache Memory Design for Scalable SMT Architectures |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
DELTA
2008
IEEE
13 years 9 months ago
2008
IEEE
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
MSS
2003
IEEE
14 years 24 days ago
2003
IEEE
zFS is a research project aimed at building a decentralized file system that distributes all aspects of file and storage management over a set of cooperating machines interconne...
IWMM
2009
Springer
14 years 2 months ago
2009
Springer
Dynamic binary instrumentation systems are used to inject or modify arbitrary instructions in existing binary applications; several such systems have been developed over the past ...