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GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 5 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
CLUSTER
2003
IEEE
14 years 22 days ago
Coordinated Checkpoint versus Message Log for Fault Tolerant MPI
— Large Clusters, high availability clusters and Grid deployments often suffer from network, node or operating system faults and thus require the use of fault tolerant programmin...
Aurelien Bouteiller, Pierre Lemarinier, Gér...
CODES
2009
IEEE
14 years 2 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles
ASC
2011
13 years 2 months ago
Autonomic fault-handling and refurbishment using throughput-driven assessment
A new paradigm for online EH regeneration using Genetic Algorithms (GAs) called Competitive Runtime Reconfiguration (CRR) is developed where performance is assessed based upon a b...
Ronald F. DeMara, Kening Zhang, Carthik A. Sharma