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DAC
2005
ACM
13 years 10 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey
ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
14 years 28 days ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard
DAC
2004
ACM
14 years 9 months ago
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
Chong Zhao, Xiaoliang Bai, Sujit Dey
MEMICS
2010
13 years 3 months ago
Monitoring and Control of Temperature in Networks-on-Chip
Abstract. Increasing integration densities and the emergence of nanotechnology cause issues related to reliability and power consumption to become dominant factors for the design o...
Tim Wegner, Claas Cornelius, Andreas Tockhorn, Dir...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee