Sciweavers

3373 search results - page 112 / 675
» Operating Systems for FPGA Based Computers and Their Memory
Sort
View
USENIX
2007
13 years 10 months ago
Virtual Machine Memory Access Tracing with Hypervisor Exclusive Cache
Virtual machine (VM) memory allocation and VM consolidation can benefit from the prediction of VM page miss rate at each candidate memory size. Such prediction is challenging for...
Pin Lu, Kai Shen
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 8 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
NCA
2008
IEEE
14 years 2 months ago
Finite Memory: A Vulnerability of Intrusion-Tolerant Systems
In environments like the Internet, faults follow unusual patterns, dictated by the combination of malicious attacks with accidental faults such as long communication delays caused...
Giuliana Santos Veronese, Miguel Correia, Lau Cheu...
ASPLOS
2011
ACM
12 years 11 months ago
RCDC: a relaxed consistency deterministic computer
Providing deterministic execution significantly simplifies the debugging, testing, replication, and deployment of multithreaded programs. Recent work has developed deterministic...
Joseph Devietti, Jacob Nelson, Tom Bergan, Luis Ce...
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 1 months ago
Worst case delay analysis for memory interference in multicore systems
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia...