599 search results - page 48 / 120 » Operator scheduling in data stream systems |
VEE
2010
ACM
14 years 2 months ago
2010
ACM
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
JSAC
2007
13 years 7 months ago
2007
— Despite its low-complexity, the zero-forcing receiver is known to suffer from noise enhancement to restore the spatially multiplexed data in a single-user MIMO system. Neverthe...
GLOBECOM
2008
IEEE
14 years 2 months ago
2008
IEEE
—Many data center devices, for instance packet switches, can be modeled within the context of resource constrained queueing systems. In this paper, we define a novel algorithm c...
MICRO
1997
IEEE
13 years 12 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
SSS
2010
Springer
13 years 6 months ago
2010
Springer
We present a distributed transactional memory (TM) scheduler called Bi-interval that optimizes the execution order of transactional operations to minimize conflicts. Bi-interval c...