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JSS
2006
104views more  JSS 2006»
13 years 7 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
VL
2005
IEEE
135views Visual Languages» more  VL 2005»
14 years 1 months ago
Easing Program Comprehension by Sharing Navigation Data
Large software projects often require a programmer to make changes to unfamiliar source code. This paper describes a set of tools, called Team Tracks, designed to ease program com...
Robert DeLine, Mary Czerwinski, George G. Robertso...
ACMICEC
2004
ACM
205views ECommerce» more  ACMICEC 2004»
14 years 1 months ago
M-Modeler: a framework implementation for modeling m-commerce applications
At the present time, the use of mobile technology in business, is becoming an opportunity to generate competitive advantages within organization environments. Mobile technology he...
Ana Hilda Morales-Aranda, Oscar Mayora-Ibarra, San...
GI
2005
Springer
14 years 1 months ago
Analysis and Design Techniques for Service-Oriented Development and Integration
: Service-Oriented Architectures (SOAs) have been established as an IT strategy to support the on demand goal of business agility. Web services standards and their implementations ...
Olaf Zimmermann, Niklas Schlimm, Günter Walle...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...