1345 search results - page 249 / 269 » Optimal Control With Noisy Time |
130
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CODES
2008
IEEE
15 years 10 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
123
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ISCA
2008
IEEE
15 years 10 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
142
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WMASH
2005
ACM
15 years 9 months ago
2005
ACM
The Session Initiation Protocol (SIP) is a popular application-level signaling protocol that is used for a wide variety of applications such as session control and mobility handli...
139
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CCGRID
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper introduces a new benchmark tool for evaluating performance and availability (performability) of networked storage systems, specifically storage area network (SAN) that...
129
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HIPC
1999
Springer
15 years 8 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...