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» Optimal Design of Signaling Networks for Internet Telephony
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FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
14 years 2 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
ICDCS
2003
IEEE
14 years 1 months ago
Neighbor Table Construction and Update in a Dynamic Peer-to-Peer Network
In a system proposed by Plaxton, Rajaraman and Richa (PRR), the expected cost of accessing a replicated object was proved to be asymptotically optimal for a static set of nodes an...
Huaiyu Liu, Simon S. Lam
ICNP
1998
IEEE
14 years 1 hour ago
A State Management Protocol for IntServ, DiffServ and Label Switching
Providing Quality of Service (QOS) in an efficient and scalable manner in the Internet is a topic of active research. The technologies that have drawn the most attention are Integ...
Hari Adiseshu, Guru M. Parulkar, Raj Yavatkar
CODES
2008
IEEE
14 years 2 months ago
Cache-aware optimization of BAN applications
Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring ...
Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mi...
DAC
1996
ACM
13 years 12 months ago
Optimal Clock Skew Scheduling Tolerant to Process Variations
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman