261 search results - page 14 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— In this paper we propose a method for lowering the power consumption in our previously proposed method for approximating elementary functions. By rearranging the interconnect o...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
DSN
2002
IEEE
14 years 15 days ago
2002
IEEE
A virtual duplex system (VDS) can be used to increase safety without the use of structural redundancy on a single machine. If a deterministic program P is calculating a given func...
VTS
2002
IEEE
14 years 13 days ago
2002
IEEE
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...