261 search results - page 40 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
111
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ICFP
2002
ACM
16 years 2 months ago
2002
ACM
We have added a Java virtual machine (henceforth JVM) bytecode generator to the optimizing Scheme-to-C compiler Bigloo. We named this new compiler BiglooJVM. We have used this new...
135
Voted
IJON
2011
14 years 6 months ago
2011
, Yunde Jia Model structure selection is currently an open problem in modeling data via Gaussian Mixture Models (GMM). This paper proposes a discriminative method to select GMM st...
90
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DATE
2009
IEEE
15 years 9 months ago
2009
IEEE
Abstract— This paper discusses the generation of informationrich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of ...
108
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DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
131
Voted
ASAP
2008
IEEE
15 years 4 months ago
2008
IEEE
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...