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INFOCOM
2006
IEEE
15 years 10 months ago
Cross-Layer Congestion Control, Routing and Scheduling Design in Ad Hoc Wireless Networks
Abstract— This paper considers jointly optimal design of crosslayer congestion control, routing and scheduling for ad hoc wireless networks. We first formulate the rate constrai...
Lijun Chen, Steven H. Low, Mung Chiang, John C. Do...
HPCA
2009
IEEE
16 years 4 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
OSDI
2008
ACM
16 years 4 months ago
R2: An Application-Level Kernel for Record and Replay
Library-based record and replay tools aim to reproduce an application's execution by recording the results of selected functions in a log and during replay returning the resu...
Zhenyu Guo, Xi Wang, Jian Tang, Xuezheng Liu, Zhil...
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
15 years 10 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
RSP
2007
IEEE
143views Control Systems» more  RSP 2007»
15 years 10 months ago
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
Ewerson Carvalho, Ney Calazans, Fernando Moraes