The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
— In the process of learning a pattern I, the Fuzzy ARTMAP algorithm templates (i.e., the weight vectors corresponding to nodes of its category representation layer) compete for ...
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgo...