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FPGA
2003
ACM
120views FPGA» more  FPGA 2003»
14 years 3 months ago
Architecture evaluation for power-efficient FPGAs
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
Fei Li, Deming Chen, Lei He, Jason Cong
SODA
2004
ACM
144views Algorithms» more  SODA 2004»
13 years 11 months ago
Covering minimum spanning trees of random subgraphs
We consider the problem of finding a sparse set of edges containing the minimum spanning tree (MST) of a random subgraph of G with high probability. The two random models that we ...
Michel X. Goemans, Jan Vondrák
PSB
2003
13 years 11 months ago
Towards Identifying Lateral Gene Transfer Events
This paper is concerned with evaluating the performance of the model and algorithm in [7] for detecting lateral gene transfers events. Using a Poisson process to describe arrival t...
Louigi Addario-Berry, Michael T. Hallett, Jens Lag...
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
14 years 2 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 3 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...