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ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 6 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
CEC
2010
IEEE
13 years 11 months ago
An analysis of massively distributed evolutionary algorithms
Computational science is placing new demands on optimization algorithms as the size of data sets and the computational complexity of scientific models continue to increase. As thes...
Travis J. Desell, David P. Anderson, Malik Magdon-...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 9 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
NETWORKS
2008
13 years 9 months ago
Decontamination of hypercubes by mobile agents
In this paper we consider the decontamination problem in a hypercube network of size n. The nodes of the network are assumed to be contaminated and they have to be decontaminated ...
Paola Flocchini, Miao Jun Huang, Flaminia L. Lucci...
COMPGEOM
2009
ACM
14 years 4 months ago
Coresets for polytope distance
Following recent work of Clarkson, we translate the coreset framework to the problems of finding the point closest to the origin inside a polytope, finding the shortest distance...
Bernd Gärtner, Martin Jaggi