402 search results - page 22 / 81 » Optimal clock synchronization in networks |
FMICS
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. TTEthernet is a communication infrastructure for mixedcriticality systems that integrates dataflow from applications with different criticality levels on a single network...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...