Sciweavers

402 search results - page 26 / 81
» Optimal clock synchronization in networks
Sort
View
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 1 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
14 years 1 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
INFOCOM
2002
IEEE
14 years 18 days ago
Power-Saving Protocols for IEEE 802.11-Based Multi-Hop Ad Hoc Networks
—Power-saving is a critical issue for almost all kinds of portable devices. In this paper, we consider the design of power-saving protocols for mobile ad hoc networks (MANETs) th...
Yu-Chee Tseng, Chih-Shun Hsu, Ten-Yueng Hsieh
NOCS
2009
IEEE
14 years 2 months ago
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
Daniele Ludovici, Alessandro Strano, Davide Bertoz...
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
14 years 1 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng