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» Optimal clock synchronization in networks
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ATVA
2006
Springer
131views Hardware» more  ATVA 2006»
13 years 11 months ago
Timed Unfoldings for Networks of Timed Automata
Whereas partial order methods have proved their efficiency for the analysis of discrete-event systems, their application to timed systems remains a challenging research topic. Here...
Patricia Bouyer, Serge Haddad, Pierre-Alain Reynie...
JSAC
2011
253views more  JSAC 2011»
13 years 2 months ago
Control Channel Establishment in Cognitive Radio Networks using Channel Hopping
Abstract—In decentralized cognitive radio (CR) networks, enabling the radios to establish a control channel (i.e., “rendezvous” to establish a link) is a challenging problem....
Kaigui Bian, Jung Min Park, Ruiliang Chen
IPPS
1997
IEEE
13 years 12 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
13 years 11 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
NOCS
2010
IEEE
13 years 5 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...