102 search results - page 7 / 21 » Optimal gradient clock synchronization in dynamic networks |
DAC
2009
ACM
14 years 2 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
EMSOFT
2010
Springer
13 years 5 months ago
2010
Springer
We propose a technique to automatically synthesize programs and schedules for hard real-time distributed (embedded) systems from synchronous data-flow models. Our technique connec...
DSN
2007
IEEE
14 years 1 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
SIAMADS
2010
13 years 2 months ago
2010
Previous numerical and analytical work has shown that synaptic coupling can allow a network of model neurons to synchronize despite heterogeneity in intrinsic parameter values. In ...