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» Optimal instruction scheduling using integer programming
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CGO
2004
IEEE
14 years 11 days ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
CF
2006
ACM
14 years 2 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
ICNP
2002
IEEE
14 years 1 months ago
An Ultra-fast Shared Path Protection Scheme - Distributed Partial Information Management, Part II
— This paper describes a novel, ultra-fast heuristic algorithm to address an NP-hard optimization problem. One of its significances is that, for the first time, the paper shows...
Dahai Xu, Chunming Qiao, Yizhi Xiong
LCTRTS
2007
Springer
14 years 2 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
DATE
2005
IEEE
171views Hardware» more  DATE 2005»
14 years 2 months ago
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space r...
Ozcan Ozturk, Hendra Saputra, Mahmut T. Kandemir, ...