979 search results - page 166 / 196 » Optimal instruction scheduling using integer programming |
EMSOFT
2007
Springer
14 years 2 months ago
2007
Springer
Most recent embedded systems use caches to improve their average performance. Current timing analyses are able to compute safe timing guarantees for these systems, if tasks are ru...
ISCA
2000
IEEE
14 years 1 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
IWOMP
2007
Springer
14 years 2 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
CPAIOR
2008
Springer
13 years 10 months ago
2008
Springer
This paper extends our previous work by exploring the use of a hybrid solution method for solving the connection subgraph problem. We employ a two phase solution method, which dras...
PDPTA
2007
13 years 10 months ago
2007
- The MASC (for Multiple Associative Computing) model is a SIMD model enhanced with associative properties and multiple synchronous instruction streams (IS). A number of algorithms...