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» Optimal instruction scheduling using integer programming
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CSREAESA
2006
13 years 11 months ago
Static Program Partitioning for Embedded Processors
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
Bageshri Sathe, Uday P. Khedker
LCTRTS
2004
Springer
14 years 3 months ago
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...
ICSM
2007
IEEE
14 years 4 months ago
Matching Control Flow of Program Versions
In many application areas, including piracy detection, software debugging and maintenance, situations arise in which there is a need for comparing two versions of a program that d...
Vijayanand Nagarajan, Rajiv Gupta, Matias Madou, X...
PADL
2004
Springer
14 years 3 months ago
Improved Compilation of Prolog to C Using Moded Types and Determinism Information
We describe the current status of and provide performance results for a prototype compiler of Prolog to C, ciaocc. ciaocc is novel in that it is designed to accept different kinds...
José F. Morales, Manuel Carro, Manuel V. He...
DATE
2008
IEEE
165views Hardware» more  DATE 2008»
14 years 4 months ago
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
Ken W. Batcher, Robert A. Walker