378 search results - page 25 / 76 » Optimal integrated code generation for VLIW architectures |
PLDI
1999
ACM
14 years 22 days ago
1999
ACM
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
CGO
2007
IEEE
14 years 2 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
ISCAPDCS
2007
13 years 9 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
CODES
2004
IEEE
14 years 5 days ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
CGO
2003
IEEE
14 years 1 months ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...