378 search results - page 5 / 76 » Optimal integrated code generation for VLIW architectures |
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
ICCD
1999
IEEE
13 years 11 months ago
1999
IEEE
The architecture of the TriMedia CPU64 is based on the TM1000 DSPCPU. The original VLIW architecture has been extended with the concepts of vector processing and superoperations. ...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...