378 search results - page 66 / 76 » Optimal integrated code generation for VLIW architectures |
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
SIGGRAPH
1997
ACM
13 years 11 months ago
1997
ACM
This paper describes the integration of the Berkeley Architectural Walkthrough Program with the National Institute of Standards and Technology’s CFAST fire simulator. The integ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
PC
2007
13 years 6 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This...