379 search results - page 12 / 76 » Optimal loop parallelization for maximizing iteration-level ... |
HICSS
1996
IEEE
13 years 11 months ago
1996
IEEE
To take advantage of recent architectural improvements in microprocessors, advanced compiler optimizations such as software pipelining have been developed 1, 2, 3, 4]. Unfortunate...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
With the increasing gap between processor speed and memory latency, the performance of data-dominated programs are becoming more reliant on fast data access, which can be improved...
JSAC
2007
13 years 7 months ago
2007
We explore the SNR-optimal relay functionality in a memoryless relay network, i.e. a network where, during each channel use, the signal transmitted by a relay depends only on the ...
COR
2011
13 years 1 months ago
2011
We consider the problem of scheduling a maximum profit selection of equal length jobs on m identical machines. Jobs arrive online over time and the goal is to determine a non-pre...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...