Sciweavers

379 search results - page 18 / 76
» Optimal loop parallelization for maximizing iteration-level ...
Sort
View
DAC
2002
ACM
14 years 8 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 9 days ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
ICPP
2002
IEEE
14 years 10 days ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
AINA
2006
IEEE
14 years 1 months ago
On Optimization and Parallelization of Fuzzy Connected Segmentation for Medical Imaging
Fuzzy Connectedness is an important image segmentation routine for image processing of medical images. It is often used in preparation for surgery and sometimes during surgery. It...
Christopher Gammage, Vipin Chaudhary
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
14 years 1 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son