379 search results - page 56 / 76 » Optimal loop parallelization for maximizing iteration-level ... |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
MIDDLEWARE
2009
Springer
14 years 1 months ago
2009
Springer
Abstract. The trend towards cloud and utility computing infrastructures raises challenges not only for application development, but also for management: diverse resources, changing...
HPDC
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
ICDCS
2007
IEEE
14 years 1 months ago
2007
IEEE
A fundamental problem in a large scale decentralized stream processing system is how to best utilize the available resources and admission control the bursty and high volume input...
PROCEDIA
2011
12 years 10 months ago
2011
Two decades of microprocessor architecture driven by quantitative 90/10 optimization has delivered an extraordinary 1000-fold improvement in microprocessor performance, enabled by...