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ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
ICRA
2008
IEEE
183views Robotics» more  ICRA 2008»
14 years 2 months ago
Hybrid image-plane/stereo (HIPS) for orientation control of manipulators
— Planetary exploration systems, operating under severe environmental and operating conditions, have thus far successfully employed carefully calibrated stereo cameras and manipu...
Kevin Nickels
NOCS
2008
IEEE
14 years 2 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
RSP
2007
IEEE
143views Control Systems» more  RSP 2007»
14 years 2 months ago
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
Ewerson Carvalho, Ney Calazans, Fernando Moraes
SECON
2007
IEEE
14 years 2 months ago
INPoD: In-Network Processing over Sensor Networks based on Code Design
—In this paper, we develop a joint Network Coding (NC)-channel coding error-resilient sensor-network approach that performs In-Network Processing based on channel code Design (IN...
Kiran Misra, Shirish S. Karande, Hayder Radha