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GLVLSI
2005
IEEE
199views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Interconnect delay minimization through interlayer via placement in 3-D ICs
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
Vasilis F. Pavlidis, Eby G. Friedman
FCCM
2002
IEEE
208views VLSI» more  FCCM 2002»
14 years 24 days ago
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
Nicholas Weaver, John Wawrzynek
HICSS
2000
IEEE
104views Biometrics» more  HICSS 2000»
14 years 7 days ago
Placement of Dispersed Generations Systems for Reduced Losses
Recent improvements in fuel cell technology along with an increasing demand for small generator units have led to renewed interest in dispersed generation units. This work demonst...
T. Griffin, K. Tomsovic, D. Secrest, A. Law
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Partitioning and placement for buildable QCA circuits
— Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chem...
Ramprasad Ravichandran, Michael T. Niemier, Sung K...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 2 months ago
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
Ganesh Venkataraman, Jiang Hu