Sciweavers

64 search results - page 7 / 13
» Optimal register assignment to loops for embedded code gener...
Sort
View
VEE
2012
ACM
238views Virtualization» more  VEE 2012»
12 years 5 months ago
Swift: a register-based JIT compiler for embedded JVMs
Code quality and compilation speed are two challenges to JIT compilers, while selective compilation is commonly used to tradeoff these two issues. Meanwhile, with more and more Ja...
Yuan Zhang, Min Yang, Bo Zhou, Zhemin Yang, Weihua...
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
14 years 2 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
CGO
2010
IEEE
14 years 5 months ago
Linear scan register allocation on SSA form
The linear scan algorithm for register allocation provides a good register assignment with a low compilation overhead and is thus frequently used for just-in-time compilers. Altho...
Christian Wimmer, Michael Franz
CASES
2006
ACM
14 years 4 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
IEEEPACT
2002
IEEE
14 years 3 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...