Sciweavers

38 search results - page 2 / 8
» Optimal reliable crosstalk-driven interconnect optimization
Sort
View
ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 4 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
DAC
2001
ACM
14 years 8 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
CN
2004
150views more  CN 2004»
13 years 7 months ago
Optimizing interconnection policies
There are two basic types of interconnection agreements between providers in the Internet: peering and transit. A decision every Internet network service provider (INSP) has to ma...
Oliver Heckmann, Jens Schmitt, Ralf Steinmetz
TCAD
2002
99views more  TCAD 2002»
13 years 7 months ago
Analysis of on-chip inductance effects for distributed RLC interconnects
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
Kaustav Banerjee, Amit Mehrotra
ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...