In this work, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical rel...
Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Ky...
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...